## Stub (存根)

用户可以清空一个层次组件结构作为存根(stub):

```Scala
class SubSysModule extends Component{
    val io = new Bundle{
        val dx = slave(Stream(Bits(32 bits)))
        val dy = master(Stream(Bits(32 bits)))
    }
    io.dy <-< io.dx
}
class TopLevle extends Component {
    val dut = new SubSysModule().stub   //实例化该模块为一个空的存根
}
```

上述代码为生成如下所示的Verilog：

```Verilog
module SubSysModule (
    input               io_dx_valid,
    output              io_dx_ready,
    input      [31:0]   io_dx_payload,
    output              io_dy_valid,
    input               io_dy_ready,
    output     [31:0]   io_dy_payload,
    input               clk,
    input               reset
);


    assign io_dx_ready = 1'b0;
    assign io_dy_valid = 1'b0;
    assign io_dy_payload = 32'h0;

endmodule
```

否则，会生成如下Verilog:

```Verilog
module SubSysModule (
  input               io_dx_valid,
  output reg          io_dx_ready,
  input      [31:0]   io_dx_payload,
  output              io_dy_valid,
  input               io_dy_ready,
  output     [31:0]   io_dy_payload,
  input               clk,
  input               reset
);

  wire                io_dx_m2sPipe_valid;
  wire                io_dx_m2sPipe_ready;
  wire       [31:0]   io_dx_m2sPipe_payload;
  reg                 io_dx_rValid;
  reg        [31:0]   io_dx_rData;
  wire                when_Stream_l368;

  always @(*) begin
    io_dx_ready = io_dx_m2sPipe_ready;
    if(when_Stream_l368) begin
      io_dx_ready = 1'b1;
    end
  end

  assign when_Stream_l368 = (! io_dx_m2sPipe_valid);
  assign io_dx_m2sPipe_valid = io_dx_rValid;
  assign io_dx_m2sPipe_payload = io_dx_rData;
  assign io_dy_valid = io_dx_m2sPipe_valid;
  assign io_dx_m2sPipe_ready = io_dy_ready;
  assign io_dy_payload = io_dx_m2sPipe_payload;
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      io_dx_rValid <= 1'b0;
    end else begin
      if(io_dx_ready) begin
        io_dx_rValid <= io_dx_valid;
      end
    end
  end

  always @(posedge clk) begin
    if(io_dx_ready) begin
      io_dx_rData <= io_dx_payload;
    end
  end


endmodule
```

也可以使用如下方式来清空顶层组件：

```Scala
SpinalVerilog(new Pinsec(500 MHz).stub)
```

Stub存根的功能总结如下：
+ 首先遍历所有组件, 找出时钟, 然后保持时钟
+ 删除所有子组件
+ 删除所有用户不想要的赋值和逻辑
+ 对所有输出端口赋值0