仿真(Simulation)

• 介绍(Introduction)
  • 一、SpinalHDL如何用Verilator仿真(How SpinalHDL simulates the hardware with Verilator backend)
  • 二、SpinalHDL如何用GHDL/Icarus仿真(How SpinalHDL simulates the hardware with GHDL/Icarus backend)
  • 三、SpinalHDL如何用Synopsys VCS仿真(How SpinalHDL simulates the hardware with Synopsys VCS backend)
  • 四、性能
• 安装指南(Installation instructions)
  • 一、Scala
  • 二、后端相关的安装指南(Backend-dependent installation instructions)
• 启动仿真(Boot a Simulation)
  • 一、介绍(Introduction)
  • 二、配置(Configuration)
  • 三、在同一硬件上运行多个测试用例(Running multiple tests on the same hardware)
  • 四、从线程中报告仿真的成功或失败(Throw Success or Failure of the simulation from a thread)
• 访问仿真信号(Accessing signals of the simulation)
  • 一、读写信号(Read and write signals)
  • 二、在模块层次访问信号(Accessing signals inside the component’s hierarchy)
• 访问仿真信号(Accessing signals of the simulation)
  • 一、读写信号(Read and write signals)
  • 二、在模块层次访问信号(Accessing signals inside the component’s hierarchy)
• 时钟域(Clock domains)
  • 一、激励API(Stimulus API)
  • 二、等待API(Wait API)
  • 三、传回API(Callback API)
  • 四、默认时钟域(Default ClockDomain)
  • 五、新时钟域(New ClockDomain)
• 满线程API(Thread-full API)
  • 一、仿真线程的分叉和汇合(Fork and Join simulation threads)
  • 二、休眠和等待(Sleep and WaitUntil)
• 少线程API(Thread-less API)
• 敏感API(Sensitive API)
• 仿真引擎(Simulation engine)
• 例子(Examples)
  • 一、异步加法器(Asychronous adder)
  • 二、双时钟FIFO(Dual clock FIFO)
  • 三、单时钟FIFO(Single clock FIFO)
  • 四、同步加法器(Synchronous adder)
  • 五、串口译码器(Uart decoder)
  • 六、串口编码器(Uart encoder)